The present invention relates generally to semiconductor devices and, more particularly, to semiconductor device manufacturing.
In a cell array region of a semiconductor device, a plurality of conductive lines for defining unit cells, for example, a plurality of word lines and a plurality of bit lines, are arranged in a predetermined direction.
FIG. 1 is a block diagram of a memory cell array 100 of a conventional NAND flash memory device, which is a type of non-volatile memory device, and an X-decoder 110 and a Y-decoder 120, which are peripheral circuits of the memory cell array 100. FIG. 2 is a circuit diagram of a structure of the memory cell array 100.
Referring to FIGS. 1 and 2, the conventional NAND flash memory device includes the memory cell array 100 which includes a plurality of memory cell blocks 100A each made up of a plurality of memory cells. The X-decoder 110 selects word lines WL0, WL1, through to WLm-1, and WLm of the memory cell blocks 100A, and the Y-decoder 120 selects bit lines BL0, BL1, through to BLn-1, and BLn of the memory cell blocks 100A. A Y-gating 130 is connected to the Y-decoder 120 and designates paths of the bit lines of the memory cell array 100.
Each of the memory cell blocks 100A of the memory cell array 100 includes a plurality of cell strings 10 formed between the bit lines BL0, BL1, through to BLn-1, BLn and a common source line CSL. Each of the cell string 10 includes a plurality of memory cells 12 connected in series. Gate electrodes of the memory cells 12 included in one cell string 10 are respectively connected to word lines WL0, WL1, through to WLm-1, and WLm. A ground selection transistor 14 connected to a ground selection line GSL is disposed on one end of each of the cell strings 10 and a string selection transistor 16 connected to a string selection line SSL is disposed on the other end of each of the cell strings 10. The ground selection transistor 14 and the string selection transistor 16 control electrical connections between the memory cells 12 and the bit lines BL0, BL1, through to BLn-1, and BLn and the common source line CSL. The memory cells 12 connected to each of the word lines WL0, WL1, through to WLm-1, and WLm across the cell strings 10 form a page unit or a byte unit.
In the NAND flash memory device of FIGS. 1 and 2, in order to perform a read operation or a write operation by selecting a predetermined memory cell, the predetermined memory cell is selected by selecting the word line WL0, WL1, through to WLm-1, and WLm and the bit line BL0, BL1, through to BLn-1, and BLn by using the X-decoder 110 and the Y-decoder 120.
A NAND flash memory device has a high integration density since the NAND flash memory device has a structure in which a plurality of memory cells are connected in series. However, recently, further reduction of the design rule of the NAND flash memory device is required in order to shrink the chip size. Also, as the design rule is reduced, the minimum pitch of patterns required for constituting the NAND flash memory device is also greatly reduced. In order to realize a minute pattern that meets the reduced design rule, various methods of forming patterns are employed. In particular, in order to realize a cell array structure of NAND flash memory devices that is difficult to realize using only exposure equipment and exposure technology that are provided by current lithography techniques, a double patterning technique for repeatedly forming a plurality of patterns by using a minute pitch that transcends the limits of conventional lithography techniques has been proposed.
In a conventional NAND flash memory device, a contact pad for connecting the word lines WL0, WL1, through to WLm-1, and WLm to the X-decoder 110 is integrally formed with the word lines WL0, WL1, through to WLm-1, and WLm. The contact pad is formed at the same time as when the word lines WL0, WL1, through to WLm-1, and WLm are formed. Thus, when the word lines WL0, WL1, through to WLm-1, and WLm are formed using the double patterning technique, a trimming process for removing undesired portions of fine patterns unnecessarily formed around the contact pad for connection to a peripheral circuit is also performed. The same trimming process is also applied to a case in which a contact pad for connecting the bit lines BL0, BL1, through to BLn-1, and BLn to the Y-decoder 120 is integrally formed with the bit lines BL0, BL1, through to BLn-1, and BLn.
However, in such a conventional NAND flash memory device, a configuration of contact pads for peripheral circuit connections connected to word lines and bit lines is minute and complicated, and thus, a layout of a mask pattern for this trimming process is complicated. In particular, the design rule of the NAND flash memory device is greatly reduced according to a recent market demand, and pattern sizes of word lines and bit lines that constitute the NAND flash memory device are becoming more minute, and accordingly, the configuration of the contact pads for peripheral circuit connections connected to the word lines and the bit lines become even more minute and complicated. Thus, the layout of a mask pattern for a trimming process is also minute and complicated. Also, since the pitch between minute patterns formed by the double patterning technique is very small, when a mask pattern for trimming is formed, a tolerance of an alignment error between the minute patterns formed by double patterning and the mask pattern is very strict. Thus, due to the possibility of misalignment occurring during performance of an aligning process and due to various parameters used in an etching process, problems such as removal of patterns in necessary regions or generation of undesired shapes of patterns after a trimming process may be generated.